The present invention relates to a semiconductor device and a manufacturing technology therefor, and particularly to technology which is effective when applied to a semiconductor device having a structure in which the bottom surface of a chip mounting portion having a semiconductor chip mounted thereover is exposed from a sealing body.
In Japanese Unexamined Patent Publication No. 2004-235217 (Patent Document 1), a semiconductor device is described in which the bottom surface of a tab (chip mounting portion) having a semiconductor chip mounted thereover is exposed from a sealing portion, and interlocking projecting portions which are bent toward the inside of the sealing portion to project are provided in a comb-like shape along the edge of the tab to inhibit the tab from coming off.
In Japanese Unexamined Patent Publication No. 2006-318996 (Patent Document 2), a semiconductor device is described in which a thinned portion is projected from around the outer periphery of a die pad (chip mounting portion), and an engagement portion such as a through hole is provided in the thinned portion to improve the adhesion between a sealing resin and the die pad.
In Japanese Unexamined Patent Publication No. 2002-100722 (Patent Document 3), a semiconductor device is described in which the peripheral portion of a tab is provided with a stepped portion, and a peripherally continuous indented portion is provided in the stepped portion to stop the advancement of peeling of a resin sealing body from the tab.
In Japanese Unexamined Patent Publication No. 2005-294464 (Patent Document 4), a semiconductor device (non-insulated-type DC-DC converter) is described in which plurality of semiconductor chips mounted over respective die pads are collectively sealed in a sealing body.